Welcome to the ECE 449 Computer Design Lab

Welcome to the ECE 449 Computer Design Lab

ECE 448 Lecture 9 Bare Metal System Software Development ECE 448 FPGA and ASIC Design with VHDL

George Mason University Required Reading P. Chu, FPGA Prototyping by VHDL Examples Chapter 9, Bare Metal System Software

Development Source Code of Examples http://academic.csuohio.edu/chu_p/rtl/fpga_mcs_vhdl.html ECE 448 FPGA and ASIC Design with VHDL

2 Software Hierarchy Desktop-like system

Bare Metal Systems Basic Embedded Program Architecture

Address Map of a Simple System I/O Register Map of a Timer Core I/O Address Map of the FPro System The subsystem provides 64 slots to connect up to 64 (i.e., 2 6)

I/O cores Each I/O core is allocated with 32 (i.e., 25) registers Each register is 32 bits wide (i.e., a word) The subsystem requires a memory space of 211 (i.e., 26 2 25) words or 213 bytes. The 11-bit word address for the MMIO subsystem appears as

sss_sssr_rrrr in which ssssss is the slot number and rrrrr is the register offset. When combined with the video subsystem, its 22-bit word address becomes 00_0000_0000_0sss_sssr_rrrr However, most I/O cores will not use all 32 registers and will not always need 32 data bits

C Pointers C Pointer to I/O Register Robust I/O Register Access

The address assignment of the FPro system is fixed for the slots in the MMIO subsystem and various modules in the video subsystem. Only two parts may change: Bridge base address Slot assignment in the MMIO subsystem

Instead of using hard literals, we express the information using symbolic constants and record them in chu_io_map.h : a C/C++ header file used for software development chu_io_map.vhd : a VHDL package declaration to be used in conjunction with hardware development

Robust I/O Register Access (cont.) The processor treats the MMIO and video subsystems as a single I/O module and communicates with the module via the bridge The bridge base address is the starting address of the module

and is assigned when a system is created For the MicroBlaze MCS configuration, it is a fixed value of 0xc0000000 For an IP core attached to the MMIO subsystem, its base address can be calculated using the assigned slot number. Recall that each slot contains 32 words (128 bytes). The base

address of slot n is Bridge_base_address + n 2 32 2 4 Slot assignment of the vanilla FPro system Slot and constant definitions

in chu_io_map.h inttypes.h C has many predefined data types, such as short, int, and long. The width (i.e., number of bits) of each data type is left to the compiler and implementation.

While interacting with low-level device activities, it is often important to know the exact width and format of registers and data. To facilitate this, C provides a header file, inttypes.h, which explicitly specifies the width and format of each data type. It is good practice to use these data types for low-level

coding. Data Types in inttypes.h

int8_t: signed 8-bit integer uint8_t: unsigned 8-bit integer int16_t: signed 16-bit integer uint16_t: unsigned 16-bit integer int32_t: signed 32-bit integer

uint32_t: unsigned 32-bit integer int64_t: signed 64-bit integer uint64_t: unsigned 64-bit integer I/O Macros in chu_io_rw.h

GpoCore class definition in gpio_core.h GpoCore class implementation in gpio_core.cpp

GpiCore class definition in gpio_core.h GpiCore class implementation in gpio_core.cpp

I/O Register Map of a Timer Core TimerCore class definition in timer_core.h

TimerCore class implementation in timer_core.cpp FPro utility routine declarations and macros in chu_init.h

FPro utility routine declarations and macros in chu_init.h FPro utility routine implementation in chu_init.cpp Vanilla FPro test program in main_vanilla_test.cpp

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