MIPS Assembly Why are we learning assembly Comparing

MIPS Assembly Why are we learning assembly  Comparing

MIPS Assembly Why are we learning assembly Comparing to higher level languages such as C, assembly languages are more difficult to write, read, and debug. have poor portability Every processor has its own assembly language. The MIPS code you write is NOT going to run on Intel processors. Then why are we learning it? After learning the first assembly language, the second will be MUCH easier It brings us closer to the processor, which is the

goal of this course. MIPS ISA There are many different Instruction Set Architectures designed for different applications with different performance/cost tradeoff Including Intel-32, PowerPC, MIPS, ARM . We focus on MIPS architecture Microprocessor without Interlocked Pipeline Stages A RISC (reduced instruction set computer) architecture In contrast to CISC (complex instruction set computer)

Similar to other architectures developed since the 1980's Almost 100 million MIPS processors manufactured in 2002 Used by NEC, Nintendo, Cisco, Silicon Graphics, Sony, 01/27/2020 CDA3100 3 A peek into the future 01/27/2020

CDA3100 4 Abstract View of MIPS Implementation 01/27/2020 CDA3100 5 MIPS Instruction Set

An instruction is a command that hardware understands Instruction set is the vocabulary of commands understood by a given computer It includes arithmetic instructions, memory access instructions, logical operations, instructions for making decisions 01/27/2020 CDA3100 6

Arithmetic Instructions Each MIPS arithmetic instruction performs only one operation Each one must always have exactly three variables add a, b, c # a = b + c Note that these variables can be the same though If we have a more complex statement, we have to break it into pieces

01/27/2020 CDA3100 7 Arithmetic Instructions Example f = (g + h) (i + j) 01/27/2020 CDA3100

8 Arithmetic Instructions Example f = (g + h) (i + j) 01/27/2020 add t0, g, h # temporary variable t0 contains g + h

add t1, i, j sub f, t0, t1 # temporary variable t1 contains i + j # f gets t0 t1 CDA3100 9 Operands of Computer Hardware In C, we can define as many as variables as we need

In MIPS, operands for arithmetic operations must be from registers MIPS has thirty-two 32-bit registers 01/27/2020 CDA3100 10 MIPS Registers 01/27/2020

CDA3100 11 Arithmetic Instructions Example f = (g + h) (i + j) #In MIPS, add can not access variables directly #because they are in memory # Suppose f, g, h, i, and j are in $s0, $s1, $s2, $s3, $s4 respectively add $t0, $s1, $s2

# temporary variable t0 contains g + h add $t1, $s3, $s4 # temporary variable t1 contains i + j sub $s0, $t0, $t1 01/27/2020 # f gets t0 t1 CDA3100

12 Memory Operands Since variables (they are data) are initially in memory, we need to have data transfer instructions Note a program (including data (variables)) is loaded from memory We also need to save the results to memory Also when we need more variables than the number of registers we have, we need to use memory to save the registers that are not used at the moment

Data transfer instructions lw (load word) from memory to a register sw (store word) from register to memory 01/27/2020 CDA3100 13 Using Load and Store Memory address in load and store instructions is specified by a base register and offset

This is called base addressing 01/27/2020 CDA3100 14 Using Load and Store How to implement the following statement using the MIPS assembly we have so far? Assuming the address of A is in

$s3 and the variable h is in $s2 A[12] = h + A[8] 01/27/2020 CDA3100 15 Specifying Memory Address Memory is organized as an array of bytes (8 bits) 01/27/2020

CDA3100 16 Specifying Memory Address MIPS uses words (4 bytes) Each word must start at address that are multiples of 4 This is called alignment restriction Big Endian 01/27/2020

CDA3100 17 Example of Endianness Store 0x87654321 at address 0x0000, byte-addressable 01/27/2020 CDA3100 18

Example of Endianness Store 0x87654321 at address 0x0000, byte-addressable 01/27/2020 CDA3100 19

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