Research plans Evaluating the suitability of FinFET technology

Research plans Evaluating the suitability of FinFET technology

Research plans Evaluating the suitability of FinFET technology for analog/RF circuits involves the following: Developing a working model for SPICE simulation based on 3-D device simulation Finding optimal device layouts for high-frequency performance Designing, fabricating test circuits (LNA, oscillator) and verifying power gain, noise, linearity Refining device models based on circuit-level measurements Comparing utility of FinFET for different applications RF CMOS performance trends Effect of technology scaling on RF performance: fT: improves with scaling (1/L for short-channel devices) fMAX: improves with scaling, but limited by strong dependence on gate resistance and parasitics FMIN: decreases with scaling for a given frequency IIP3: Id/W must increase to maintain good linearity Can a sub-100nm advanced transistor structure (FinFET) take advantage of these scaling trends and confer additional benefits to analog/RF circuits, e.g. better noise performance, improved gmro? H ig h - fr e q u e n c y m o d e lin g Im p a c t o f g a t e r e s is t a n c e o n R F p e r fo r m a n c e

if ig n o r e d , p o t e n t ia l e r r o r in im p e d a n c e m a tc h in g ( e . g ., to a 5 0 - s o u rc e ) in c r e a s e d m in im u m n o is e fig u r e r e d u c e d p o w e r g a in , d e g r a d e d o v e r a ll tr a n s c o n d u c ta n c e fM A X fT 8 C gd R gate G a te r e s is t a n c e m o d e lin g R g a te c o n s is ts o f tw o c o m p o n e n ts : d is tr ib u t e d g a t e e le c tr o d e r e s is t a n c e c h a n n e l- in d u c e d g a te r e s is ta n c e

M in im iz e g a t e r e s is t a n c e b y u s in g g a te c o n ta c ts o n b o th e n d s p r o p e r la y o u t ( s h o r t m u lti- g a t e f in g e r s tr u c tu r e s ) s ilic id e d p o ly - g a te /m e ta l g a t e te c h n o lo g ie s S o u r c e : J in , IE D M 9 8 F in F E T s tr u c tu r e a n d la y o u t T h e d o u b le - g a t e F in F E T a p r o m is in g c a n d id a t e to c o n t in u e C M O S s c a lin g d e e p in t o t h e n a n o m e te r r e g im e G a t e s t r a d d le s t h in s ilic o n f in , f o r m in g t w o c o n d u c t in g c h a n n e ls o n s id e w a ll S o u rc e G ate L e n g th = L G ate g G a te 2 S o u rce C u rre n t F lo w

D r a in G a te 1 3 D v ie w o f F in F E T F in H e i g h t = H F in W id th W D r a in fin fi n = W = T S i L a y o u t s im ila r t o c o n v e n t io n a l S O I M O S F E T S o u rc e G a te S o u rce G a te

D r a in D ra in S o u rc e C o n v e n tio n a l S O I M O S F E T S o u rce M u lt i - f i n la y o u t S o u r c e ( a ll im a g e s ) : T - J K i n g , e t a l, F i n F E T T e c h n o lo g y O p t i m iz a t io n p r e s e n t a t io n s l id e s , O c t . 2 0 0 3 Future work FinFET modeling Run 3-D device simulations using ISE DESSIS Need a suitable SPICE model for initial design based on to extract high-frequency Y-parameters transistor I-V, C-V, and AC (S-parameter) characteristics Can wesimulations obtain measured S-parameter data? Initial based on BSIMSOI3.1 using preliminary SPAWAR model.

BSIM DG SPICE currently Consider how best to(DC) build an adequate under development. model (AC) based on device simulation results Need to verify high-frequency behavior of SPICE model With a working SPICE model, estimate important BSIMSOI3.1 includes RF functionality and has been high-frequency figures of merit and begin to incorporated into spice3 design basic analog/RF circuits for system-level How to obtain RF model parameters? verification of power gain, noise, linearity calibrate 3D device simulation (ISE) Extract and compare Y11, Y12, ... BSIMSOI RF model (RgateMod =3) RF model parameters

(XRCRG1, XGW,) SPICE simulation (BSIMSOI3.1) Source: BSIMSOI3.1 Manual Future work Run 3-D device simulations using ISE DESSIS to extract high-frequency Y-parameters Can we obtain measured S-parameter data? Consider how best to build an adequate SPICE model (AC) based on device simulation results With a working SPICE model, estimate important high-frequency figures of merit and begin to design basic analog/RF circuits for system-level verification of power gain, noise, linearity Application of FinFET Technology to Analog/RF Circuits Matthew Muh, Professor Ali M. Niknejad

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