Lecture 9: FPGAs vs. ASICs Spectrum of Design Choices Fast, Inflexible Choices Full Custom Polygons
ASIC Standard Cells (LTE Modem) FPGA Logic Network (Intel/Altera, Xilinx)
Specialized Processor Program (e.g., GPUs) GP Processor Program (e.g., Intel x86, ARM) Slow, Flexible
2 General FPGA Layout Wires (Routing) implemented by programming connectivity boxes (CBs) and switch boxes (SB) Logic gates implemented by programming configurable logic blocks (CLBs)
Modern FPGAs have more than 1 million equivalent logic gates 3 Configurable Logic Blocks Basic CLB comprises Lookup Table (LUT) and D-Flip Flop The MUX allows selection of either the LUT output or the D-FF output
4 Lookup Tables (LUTs) Combinational functions created with programmed tables connected to cascaded multiplexers LUT inputs are MUX select lines Programmed Levels (EEPROM or SRAM)
1 0 0 0 1 0 0 0 1
0 0 0 1 0 0 1 5
Intel Stratix II FPGA Architecture The basic Adaptive Logic Module (ALM) Block Diagram Note the fast adder carry chain (does not require going out to programmable switch boxes) 6 ALM Flexibility
Each ALM can be configured to one or two logic functions 7 ALM Flexibility 8 ALM Flexibility
9 Connectivity Between ALMs 10 Latest Stratix 10 Intel Stratix 10 GX 5500/SX 5500 FPGAs implemented in
14 nm process Contains 1,867,680 ALMs, which can implement roughly 5,510,000 logic elements (logic gates). Contains 7,470,720 ALM registers Also contains Quad ARM Cortex-A53 CPU cores 11 Integrated Quad ARM Cores
12 Many Built-In Interfaces Modern FPGAs have many built-in interfaces.
DRAM PCI Express USB SATA (disk drives) etc Makes them easy to
integrate into compute environments 13 FPGA vs. ASIC ASICs ASIC (Application-Specific Integrated Circuit) designs are
usually implemented using standard cells Standard cells are pre-designed layouts of transistors for implementation of common logic gates and registers (DFlip Flops) Standard cells are be pre-characterized in terms of cell area, cell delay, and cell power consumption Simplifies design flow, design verification, and timing analysis 15
CMOS N-Channel MOS (NMOS) transistors turn ON when the Gate voltage = 1 Gate 1 Drain Source
P-Channel MOS (PMOS) transistors turn ON when the Gate voltage = 0 Gate Source 0 Drain
16 CMOS Inverter Layout Figure derived from slides by S. Edwards from his CSEE4840 class 17 CMOS NAND Gate
Figure derived from slides by S. Edwards from his CSEE4840 class 18 CMOS NAND Gate Figure derived from slides by S. Edwards from his CSEE4840 class
19 CMOS NAND Gate Figure derived from slides by S. Edwards from his CSEE4840 class 20 CMOS NAND Gate
Figure derived from slides by S. Edwards from his CSEE4840 class 21 Standard Cells of Logic Gates 22
CMOS D-Flip Flop 23 Standard Cell of D-Flip Flop Edge-Triggered D-Flip Flop with Asynchronous Reset 24
Standard Cell Layout 25 Standard Cell Layout 26 Standard Cell Layout
27 Latest NVIDIA GPU NVIDIA Tesla GV100 GPU in 12 nm process Contains 23 billion transistors 28
Design Flows FPGA and ASIC have similar design flows FPGA Flow SystemVerilog Translation ASIC Flow SystemVerilog Translation
Logic Optimization Logic Optimization Logic Clustering to LUTs Technology Mapping
to Standard Cells Floorplanning Assignment & Programming CLBs Placement Routing &
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